1. Field of the Invention
This invention relates generally to semiconductor FET (Field Effect Transistor) device fabrication techniques, and particularly to a method and structure for forming self-aligned, borderless contacts for strain-engineered logic devices.
2. Description of Background
Structures in semiconductor devices such as FET devices may be fabricated on silicon wafers. The overlays used in fabrication methods often require a minimum distance border between a source and drain diffusion (S/D) area and a gate conductor to prevent the shorting of the gate conductor to the S/D during the fabrication process. The bordering distance is undesirable because the areas used for the contact borders result in wasted space on the silicon wafer.
Thus, it is desirable to fabricate a self-aligned structure for semiconductor devices that may be easily etched, limits the border distance between structures, and is compatible with nitride stress liners.